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This item may be a floor model or store return that has been used. See all condition definitions opens in a new window or tab. Accordingly, if a matching hash index is detected within the binary CAM during an NFA or search operation, the asserted binary CAM match signal enables the corresponding row of the memory array to be sensed by the sense amplifiers banks within the read write circuit and provided to the output logic During an insert operation or other write operation , a row address RA output from an address selector is decoded within the binary CAM to generate the decoded row address If the insert operation involves loading a new hash index into the binary CAM , the hash index is loaded into the binary CAM row indicated by the decoded row address If the insert operation involves loading a new entry into a partially filled row of the memory array that is, a row for which a corresponding hash index is already stored in the binary CAM , a hash index is not stored in the binary CAM In either case, the decoded row address is selected by the multiplexer to activate the corresponding word line within the memory array and thereby enable an entry to be stored within the indicated storage row.
The block index is fed back to the address selector to update selected address registers therein. It should be noted that, instead of outputting a decoded address to the memory array , a separate address decoder may be provided to receive an encoded address from binary CAM , and to decode the encoded address to activate the indicated word line within the memory array In such an embodiment, the multiplexer may receive the row address output by the address selector i.
During an NFA or search operation, the binary CAM index is selected to address the memory array , and during other operations e. Accordingly, the address selector , in addition to outputting the row address to the binary CAM , also outputs a segment address SA to the read write circuit As in the embodiment of FIG. In an alternative embodiment, an unsegmented memory array i. Also, while memory array is described below as having four segments and corresponding numbers of supporting circuits, more or fewer segments may be included within the memory array in alternative embodiments.
Further, in a single segment embodiment, compare logic e. The address decoder is coupled to receive the row address from the address selector , and decodes the row address to activate an indicated one of word lines The signals carried on word lines constitute the decoded row address and are output from the binary CAM as shown. The binary CAM array includes a plurality of rows of CAM cells each including a storage element and a compare circuit to enable an input hash index to be simultaneously compared with the contents of each binary CAM row.
Thus, the binary CAM index is a row address that corresponds to a row of CAM cells within the binary CAM array that contain a hash index that matches the input hash index In one embodiment, the binary CAM priority encoder is a multiplexer circuit that selects one of a plurality of row address values according to which of the binary CAM match signals , if any, is asserted during a binary CAM search operation.
In an alternative embodiment, the binary CAM priority encoder is a lookup table e. Note that, in an embodiment of the binary CAM in which only one of binary CAM match signals is asserted for a given search i. The encoder circuit may be implemented, for example, by a multiplexer circuit or a lookup table as discussed above. During a load operation in the binary CAM , a hash index is stored within a selected row of CAM cells within the binary CAM array , and validity values for each of the CAM rows are output on the match lines to indicate whether the corresponding row of CAM cells within the binary CAM array are occupied.
If the validity values indicate that all the rows of the binary CAM array are occupied by valid hash indices, the binary CAM array is full, and the binary CAM flag is deasserted to indicate the full condition. The binary CAM priority encoder also operates on the validity signals to generate a binary CAM index that is indicative of a next free address within the binary CAM array That is, the binary CAM priority encoder generates an address of the highest priority location within the binary CAM array indicated to be unoccupied by a corresponding validity signal.
As discussed below, if no match is detected within the binary CAM array during a subsequent NFA operation, the address value within the NFBA register is selected by multiplexer to be output as row address and is selected by output logic of FIG. The address selector additionally includes a partially filled row PFR register , a highest priority match HPM register and an address counter CNTR , all of which are used to store address values.
The partially filled row register is used to store the block index generating during a NFA operation that indexes a partially filled row i. The HPM register is used to store the block index generated during a search operation that results in a match detection. Address counter may be selected by multiplexer to provide a sequence of ascending or descending indices to the binary CAM and memory array , for example, to enable the binary CAM and memory array to be sequentially loaded with entries e.
The address selector outputs the row address portion RA of the selected address to the address decoder within the binary CAM and also to the output logic of FIG. As discussed above, the segment address is used to control access to individual segments within the memory array during insert, read and other memory access operations. The output logic includes compare logic circuits 1 - 4 , flag logic , segment priority logic and segment index encoder , all of which perform the same general functions as corresponding circuit blocks within the output logic of FIG.
Also, like the output logic of FIG. The binary CAM flag is input to the segment priority logic and also to the flag logic and segment index encoder The binary CAM index and row address are alternatively selected to be the row index component of the block index depending upon whether the binary CAM flag is asserted. Thus, if during a NFA operation, no match is found within the binary CAM meaning that the hash index has not previously been stored in the binary CAM , the binary CAM flag is not asserted and the multiplexer selects the next free binary CAM address to be the row index If the binary CAM flag is asserted during the NFA operation meaning that the hash index has previously been stored within the binary CAM , the binary CAM index is indicative of the location of a matching hash index within the binary CAM and is selected to be the row index During a search operation, each segment flag indicates whether the content of the corresponding segment matches the search key or portion thereof.
The flag logic receives the segment flags SF 1 -SF 4 and entry size signals, x 1 , x 2 and x 4 as inputs and includes the logic gates , , , , , , , and described above in reference to FIG. Logic gates , and operate as described in reference to FIG. Because the segment flags are only meaningful if a binary CAM match was detected during a search or NFA operation otherwise, no match signal was asserted by the binary CAM to select an entry to be input to the output logic and if the CAM block is allocated to the entry type pool or insertion pool indicated by the corresponding search or NFA instruction, the output of logic OR gate is ANDed with the binary CAM match flag and the block select signal in AND gate Logic gates , , , and also operate as described in reference to FIG.
The flag logic includes an additional path for assertion of the block flag in the event that the binary CAM flag is not asserted during a NFA operation, but the binary CAM is not full. Accordingly, so long as the binary CAM is not full, the new hash index i.
AND gate will drive the partial fill bit high if any of the segment flags SF 1 -SF 4 indicate an empty segment. By this arrangement, the fill counter indicates the number of rows within the memory array which are at least partially filled.
As discussed above, different fill measures may be used in alternative embodiments, and the fill count may be omitted from the insert priority value altogether. The segment index encoder operates similarly to the segment index encoder of FIG.
Thus, if no match is found within the binary CAM during a NFA operation, any subsequent insertion into the memory array will occur within a completely unfilled row and therefore will be directed to a predetermined segment of the row in this example, the segment indicated by segment address 00b. Note that, in an alternate embodiment, the binary CAM flag may be inverted, then logically ORed with index select signal IS 1 to achieve the same result achieved by the addition of multiplexer If such a storage row is detected, the overflow CAM outputs a predetermined priority value and asserts its block flag.
This operation of the overflow CAM is discussed below in greater detail. The block index that corresponds to the block identifier is selected as the block index component of the device index i.
At , the block identifier and selected block index are output as the device index DIN , and the device flag is generated, for example, by ORing the block flags from the hash CAM blocks and the overflow CAM block. If the device flag is not asserted, the hash CAM device is unable to store the entry If the device flag is asserted, the entry is inserted at the CAM block and memory location indicated by the device index The entry may be inserted at the indicated location without further host instruction i.
If the class code does not match the entry type or the mask code does not match the key mask, the block flag is deasserted at and the NFA operation within the hash CAM block is concluded. If the class code matches the entry type and the mask code matches the key mask, a key is generated at and used to generate a hash index HI i at At , the binary CAM is searched for a match with the hash index generated at If a matching hash index is detected within the binary CAM at , the corresponding row of the memory array is output to the output logic to determine whether the row is full If the row is not full, a partially filled row has been detected.
Accordingly, at , the binary CAM fill count is output as the block priority value the partial fill bit being cleared to 0 , the block flag is asserted, and the binary CAM index BCIN and segment index i. If the row is full, the hash CAM block is conflicted and the block flag is deasserted at If the binary CAM is full, the block flag is deasserted at If the binary CAM is not full, then at the binary CAM fill count and a logic high partial fill bit indicated by the summation of hex and the fill count in the example of FIG.
If the binary CAM flag is set, then a matching hash index was located within the binary CAM and, at , the entry is stored in the hash CAM block memory at the row and segment indicated by block index component of the NFA-generated device index. If the class code does not match the entry type, the block flag is deasserted at and the search operation within the hash CAM block is concluded. If the class code matches the entry type, a key is generated at and used to generate a hash index HI i at If a matching hash index is detected within the binary CAM at , the contents of the corresponding row of the memory array are output to the output logic for comparison with the search key If, at , the row of the memory array is determined to contain a valid entry that matches the search key, then a match has been detected.
Accordingly, at , the block flag for the hash CAM device is asserted e. If row does not contain a valid entry that matches the search key, then the block flag is deasserted at to indicate that no match was detected.
More or fewer segments may be provided in alternative embodiments, and the tag segment may be omitted. Each of the CAM cells includes storage for at least one data bit, and a compare circuit to compare the data bit with a corresponding bit of a search key One or more of the row segments may also include a different number of CAM cells than others of the row segments.
For example, in one embodiment, the tag segment includes four CAM cells to store three tag bits and a validity bit, while each of the entry segments, S 1 -S 4 , includes more than three CAM cells.
The CAM array can be configured into different width by depth configurations by programming an entry size value into the configuration register The entry size information is output as a set of one or more signals CFG to configuration dependent circuit blocks within the overflow CAM block In the exemplary embodiment shown in FIG.
Also, other types of configuration information may be programmed within configuration register in alternative embodiments. A priority value may be loaded into the priority index table e. In the x 1 configuration, for example, entries stored within segments S 1 -S 4 of a given row of the CAM array correspond to priority values stored within priority storage circuits P 1 -P 4 in the priority index table In one embodiment, the priority values used in the x 1 , x 2 and x 4 configurations are the same size i.
Consequently, in the x 1 embodiment, each of the four priority storage circuits P 1 -P 4 is used to store a priority value that corresponds to an entry in a corresponding one of entry segments S 1 -S 4 , while in the x 2 configuration, only two of the priority storage circuits are used to store priority values i. In the x 2 and x 4 configurations, the unused priority circuits may be disabled or loaded with null data e.
In alternative embodiments, differently sized priority values may be used for different CAM array configurations, and all or a portion of one priority storage circuit may be concatenated with another priority storage circuit to enable storage of larger sized priority values. The priority values stored within the priority index table indicate the relative priorities of corresponding entries within the CAM array and may be assigned in ascending priority order or descending priority order.
During a search operation, search key is simultaneously compared with all the entries within the CAM array to generate a set of match signals 1 - Y , each indicating whether an entry or entries within a corresponding row of the CAM array matches the search key The priority values within the priority index table that correspond to key-matching entries within the CAM array i.
The highest priority match-qualified priority value is output from the priority index table as a search priority value SP and is received by the priority select logic The priority select logic selects, according to the state of NFA signal , either the search priority value or an insert priority value to be output as the block priority value More specifically, during an NFA operation, when the NFA signal is high, the priority select logic outputs an insert priority value, and during a search operation, when the NFA signal is low, the priority select logic outputs the search priority value The priority index table additionally outputs a set of qualified match signals to the priority encoder and match flag logic Each of the qualified match signals corresponds to a row of the priority index table and therefore to a row of CAM array and is asserted if a match qualified priority value equal to the search priority value is stored in the priority index table row.
The priority index table includes a segmented priority number storage array referred to herein as a priority array , tag logic circuits 1 - Y , column priority logic , and row logic circuits 1 - Y.
During a search or insert operation in the CAM array, the priority index table receives Y sets of match signals 1 - Y from the CAM array and generates Y corresponding sets of qualified match signals 1 - Y in accordance an operation select signal, OPSEL generated, for example, by the instruction decoder of FIG. Each of the Y tag logic circuits receives a respective match signal from a corresponding row of the CAM array.
In one embodiment, each of the match signals includes five component match signals MT and M 1 -M 4 , that correspond to the tag segment and entry segments S 1 -S 4 , respectively. Each of the tag logic circuits 1 - Y outputs a respective set of four tag match signals, TM 1 -TM 4 , with each of the tag match signals being asserted if 1 a tag value stored in the tag segment matched a class code value associated with the search key i.
The entry size information, CFG , is input to the tag logic circuits 1 - Y to qualify the detection of a match condition. During a compare operation, each row of priority storage circuits receives a respective set of four tag match signals, TM 1 -TM 4 from a corresponding tag logic circuit and outputs a corresponding set of four prioritized match signals PM 1 -PM 4. Each asserted tag match signal is used within the priority array to enable a corresponding priority storage circuit to participate in a priority value compare operation with other such enabled priority storage circuits within the same column of priority storage circuits the enabled priority storage circuit and priority value stored therein being referred to herein as a match-selected priority storage circuit and match-qualified priority value, respectively.
The priority value compare operation within each column of priority storage circuits i. As an example, if, during a compare operation, there is a match-qualified priority value within each of the four columns of priority storage circuits of the priority array , then four column priority values will be output from the priority array to the column priority logic , and at least four prioritized match signals will be asserted i.
More than one prioritized match signal may be asserted for a given column if the column contains more than one match-qualified priority value equal to the column priority value, thus providing a potential source of multiple-match indications.
Each priority storage circuit includes a chain of n priority cells, with each cell including a compare circuit , isolation circuit and storage element Each compare circuit is connected in a wired-OR configuration with the other compare circuits in its respective column by one of priority signal lines 1 - n.
Each priority signal line may be pre-charged towards a power supply voltage or any other predetermined voltage by a pre-charge circuit Each compare circuit may be any digital or analog compare circuit that compares the priority value bit stored in the corresponding storage element with the priority value bits stored in every other storage element of the same column i. Additionally, each compare circuit monitors the comparison result of the more significant priority value bits through the logical states of match line segments Match line segments are coupled between match lines that carry incoming tag match signals TM 1 1 -TM 1 Y and match lines that carry outgoing prioritized match signals PM 1 1 -PM 1 Y by isolation circuits The isolation circuits isolate the comparison results generated for less significant priority bit locations from affecting the comparison results generated for more significant priority bit locations.
The isolation circuits may also work together with the comparison circuits to control the state of the match line segments The operation of priority index table can be illustrated with an example shown in FIG. For other embodiments, any numbers of rows and columns can be used.
Row one stores priority number having the decimal equivalent of the number 6, and row two stores priority number having the decimal equivalent of the number 5. For this example, the corresponding row of the CAM array contains segment entries that result in assertion of tag match lines TM 1 and TM 2.
Also, for this example, the priority numbers are stored in ascending priority order such that is the more significant i. Compare circuits 1,1 - 4,2 determine that is the more significant priority value, and cause PM 1 2 to be asserted as follows. The most significant bit CP 1 4 is resolved first. When any memory element stores a logic zero and the corresponding match line segment is asserted, the corresponding priority signal line is discharged.
Thus, each of compare circuits 4,2 and 4,1 discharge signal line 4 such that CP 1 4 is a logic zero. Additionally, compare circuit 4,2 compares the state of priority signal line 4 with the priority number bit stored in 4,2 , and determines that both have the same logic state.
This causes compare circuit 4,2 not to affect the logical state of match line segment 3,2 such that match line segment 3,2 has the same logic state as match line segment 4,2 TM 1 2. Similarly, compare circuit 4,1 compares the state of priority signal line 4 with the priority number bit stored in 4,1 and determines that both have the same state. This causes compare circuit 4,1 not to affect the logical state of match line segment 3,1 such that match line segment 3,1 has the same logic state as match line segment 4,1 TM 1 1.
The next most significant bit CP 1 3 is then resolved. Memory elements that store a logic one do not discharge their corresponding priority signal lines Since memory elements 3,2 and 3,1 both store logic one states, signal line 3 remains pre-charged such that CP 1 3 is a logic one.
Additionally, compare circuit 3,2 compares the state of priority signal line 3 with the priority number bit stored in 3,2 , and determines that both have the same logic state. This causes compare circuit 3,2 not to affect the logical state of match line segment 2,2 such that match line segment 2,2 has the same logic state as match line segment 3,2.
Similarly, compare circuit 3,1 compares the state of priority signal line 3 with the priority number bit stored in 3,1 and determines that both have the same logic state. This causes compare circuit 3,1 to not affect the logical state of match line segment 2,1 such that match line segment 2,1 has the same logic state as match line segment 3,1.
CP 1 2 is resolved next. Since memory element 2,2 stores a logic zero and match line segment 2,2 is asserted, compare circuit 2,2 discharges priority signal line 2.
This causes CP 1 2 to be a logic zero. Additionally, compare circuit 2,2 compares the logic zero state of priority signal line 2 with the logic zero stored in 2,2 and allows match line segment 1,2 to have the same state as match line segment 2,2.
Compare circuit 2,1 , however, compares the logic zero on priority signal line 2 with the logic one stored in memory element 2,1 , and de-asserts match line segment 1,1. When a match line segment is de-asserted, all subsequent compare circuits for that row will de-assert the remaining match line segments of the row such that the corresponding prioritized match signal PM 1 1 will be de-asserted. When the prioritized match signal is de-asserted for a particular segment, this indicates that the most significant priority number is not stored in that segment.
Additionally, when the remaining match line segments are de-asserted for a row, the compare circuits for that row do not discharge the remaining priority signal lines regardless of the logic states stored in the corresponding memory elements of that row.
For example, compare circuit 1,1 does not discharge priority signal line 1 even though memory element 1,1 stores a logic zero. Additionally, isolation circuits 4,1 , 31 , and 2,1 isolate the de-asserted match line segment 1,1 from match line segment 4,1 , 3,1 , and 2,1 such that CP 1 4 , CP 1 3 , and CP 1 2 are not affected by the de-assertion of match line segment 1,1.
Lastly, the least significant bit CP 1 1 is resolved. Compare circuit 1,2 alone determines CP 1 1 since compare circuit 1,1 cannot discharge priority signal line 1. Since memory element 1,2 stores a logic one and match line segment 1,2 is asserted, compare circuit 1,2 leaves priority signal line 1 pre-charged, and CP 1 1 is a logic one. Additionally, compare circuit 1,2 allows prioritized match signal PM 1 2 to have the same state as match line segment 1,2.
Since match line segment 1,2 is asserted, PM 1 2 will be asserted indicating that the most significant priority number is stored in that row. Thus, when thee priority comparison is completed, bits CP 1 4 -CP 1 1 indicate that the most significant priority number stored in the priority index table is , and prioritized match signal PM 1 2 is asserted to signal that is stored in row two.
For the example described above with respect to FIG. For another embodiment, the priority numbers are stored in descending priority order such that is the most significant priority number between and Table 2 shows one example of a truth table for implementing each compare circuit , where X column and Y row are any integers. Other truth tables may be used and corresponding logic generated accordingly including those that logically complement one of more or the signals indicated in Table 2.
Any logic or circuitry may be used to implement the truth table of Table 2. The priority cell includes compare circuit , isolation circuit , and memory element Compare circuit is one embodiment of compare circuit , and isolation circuit is one embodiment of isolation circuit The priority cell may be used to implement all the priority cells in the priority index table.
Provides excellent discharge characteristics. Quick delivery for every order. If you need any help or have any questions, please feel free to contact us. Size: x 85 x 25 mm Color: black Voltage: 8. Shop at Onebattery. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
However, there is no guarantee that interference will not occur in a particular installation.
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